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rev. 2.4 7/08 copyright ? 2008 by silicon laboratories si5321-xc3 si5321-xc3 sonet/sdh p recision c lock m ultiplier ic features applications description the si5321 is a precision clock multiplier that exceeds the requirements of high-speed communication systems incl uding oc-192/oc-48 and 10 gigabit ethernet. this device phase locks to an input clock in the 19, 39, 78, 155, 311, or 622 mhz frequency range and generates a frequency-multiplied clock output that can be configured for operation in the 19, 39, 78, 155, 622, 1244, or 2488 mhz frequency ra nge. silicon laboratories dspll? technology provides pll functionality with unparalleled performa nce. it eliminates external loop filter components, provides programmable lo op parameters, and simplifies design. fec rates are supported by selectable forward and reverse 255/238 (15/14), 255/237 (85/79), and 66/64 (33/32) conversion factors. the itu-t g.709 255/ 237 rate and the ieee 802 .3ae 66/64 rate are su pported when using a 155 mhz or higher rate input clock. th e performance and integration of silicon laboratories? si5321 clock ic provides high-level support of the latest specifications and systems. it operates from a single 3.3 v supply. functional block diagram ? ultra-low jitter clock output with jitter generation as low as 0.3 ps rms ? no external components (other than a resistor and bypassing) ? input clock ranges at 19, 39, 78, 155, 311, or 622 mhz ? output clock ranges at 19, 39, 78, 155, 311, 622, 1244, or 2488 mhz ? maximum range includes 693 mhz for 10 gbe fec support ? digital hold for loss-of-input clock ? support for 255/238 (15/14), 255/237 (85/79), and 66/64 fec scaling (itu-t g.709 and ieee 802.3ae) ? selectable loop bandwidth ? loss-of-signal alarm output ? low power ? small size (9x9 mm) ? backwards compatible with si5320 ? sonet/sdh line/port cards ? terabit routers ? core switches ? digital cross connects infrqsel[2:0] frqsel[2:0] cl ko ut + cl ko ut ? 2 cal_actv 2 fec[2:0] bwsel[1:0] 3 2 biasing & supply regulation rext vsel33 v d d gnd dh_act v signal detect cal i b rati on rst n/ cal 2 cl ki n+ cl ki n? valtime los fxddelay bwboost dspll? ordering information: see page 29. si5321 si5321
si5321-xc3 2 rev. 2.4
si5321-xc3 rev. 2.4 3 t able of c ontents s ection p age 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical application schema tic (3.3 v supply) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.1. dspll? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2. clock input and output rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.3. pll performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4. loss-of-signal alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.5. digital hold of the pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.6. hitless reco very from digital hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.7. reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.8. pll self-calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.9. bias generation circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 3.10. differential input ci rcuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11. differential output circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12. power supply connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.13. design and layout guid elines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4. pin descriptions: si5321 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6. package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7. 9x9 mm cbga card lay out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
si5321-xc3 4 rev. 2.4 1. electrical specifications table 1. recommended operating conditions parameter symbol test condition min 1 typ max 1 unit ambient temperature t a ?40 2 25 85 c si5321 supply voltage 3 , 3.3 v supply v dd33 3.135 3.3 3.465 v notes: 1. all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at nominal supply voltages and an operating temperature of 25 c unless otherwise stated. 2. the si5321 is guaranteed to operate and meet all electrical specifications over an ambi ent temperature of ?40 to 85 c. 3. the si5321 specifications are guarant eed when using the recommended application circuit (including component tolerance) shown in "2. typical application schematic (3 .3 v supply)" on page 15. 3.3 v operation uses an on-chip voltage regulator and is recommended.
si5321-xc3 rev. 2.4 5 figure 1. clkin voltage characteristics figure 2. rise/fall time measurement figure 3. transitionless period on clkin for detecting a los condition note: w hen using single-ended clock sources, the unused clock input on the si5321 must be ac-coupled to ground. 0.5 v id clkin+ clkin? (clkin+) ? (clkin?) v id b. operation with differential clock input v is a. operation with single-ended clock input* clkin+ clkin? note: transmission line termination, when required, must be provided externally. t f t r 80% 20% t los (c lkin+) - (c lkin - ) 0 v
si5321-xc3 6 rev. 2.4 table 2. dc characteristics, v dd =3.3v (v dd33 =3.3v 5%, t a =?40to 85c) parameter symbol test condition min typ max unit supply current 1 i dd 622.08 mhz in, 19.44 mhz out ? 141 155 ma supply current 2 i dd 19.44 mhz in, 622.08 mhz out ? 135 145 ma power dissipation using 3.3 v supply clock output p d 19.44 mhz in, 622.08 mhz out ? 445 479 mw common mode input voltage 1,2,3 (clkin) v icm 1.0 1.5 2.0 v single-ended input voltage 2,3,4 (clkin) v is see figure 1a 200 ? 500 4 mv pp differential input voltage swing 2,3,4 (clkin) v id see figure 1b 200 ? 500 4 mv pp input impedance (clkin+, clkin?) r in ?80?k differential output voltage swing (clkout) v od 100 load line-to-line 750 825 1100 mv pp output common mode voltage (clkout) v ocm 100 load line-to-line 1.4 1.8 2.2 v output short to gnd (clkout) i sc(?) ?60 ? ? ma output short to v dd25 (clkout) i sc(+) ?15?ma input voltage low (lvttl inputs) v il ??0.8v input voltage high (lvttl inputs) v ih 2.0 ? ? v input low current (lvttl inputs) i il ??50 a input high current (lvttl inputs) i ih ??50 a internal pulldowns (lvttl inputs) i pd ??50 a input impedance (lvttl inputs) r in 50 ? ? k output voltage low (lvttl outputs) v ol i o =0.5ma ? ? 0.4 v output voltage high (lvttl outputs) v oh i o =0.5ma 2.0 ? ? v notes: 1. the si5321 device provides weak 1.5 v internal biasing that enables ac-coupled operation. 2. clock inputs may be driven differentially or single-endedly. when driven single-endedly, the unused input should be ac- coupled to ground. 3. transmission line termination, when required, must be provided externally. 4. although the si5321 device can operate with input clock swings as high as 1500 mv pp , silicon laboratories recommends maintaining the input clock amplitude below 500 mv pp for optimal performance.
si5321-xc3 rev. 2.4 7 table 3. ac characteristics (v dd33 =3.3v 5%, t a = ?40 to 85 c) parameter symbol test co ndition min typ max unit input clock frequency (clkin) fec[2:0] = 000 (non fec) infrqsel[2:0] = 001 infrqsel[2:0] = 010 infrqsel[2:0] = 011 infrqsel[2:0] = 100 infrqsel[2:0] = 101 infrqsel[2:0] = 110 f clkin no fec scaling 19.436 38.872 77.744 155.48 310.97 621.95 ? ? ? ? ? ? 21.685 43.369 86.738 173.48 346.95 693.90 mhz input clock frequency (clkin) fec[2:0] = 001 (forward fec) infrqsel[2:0] = 001 infrqsel[2:0] = 010 infrqsel[2:0] = 011 infrqsel[2:0] = 100 infrqsel[2:0] = 101 infrqsel[2:0] = 110 f clkin 255/238 fec scaling 18.142 36.284 72.568 145.13 290.27 580.54 ? ? ? ? ? ? 20.239 40.478 80.955 161.91 323.82 647.64 mhz input clock frequency (clkin) fec[2:0] = 010 (reverse fec) infrqsel[2:0] = 001 infrqsel[2:0] = 010 infrqsel[2:0] = 011 infrqsel[2:0] = 100 infrqsel[2:0] = 101 infrqsel[2:0] = 110 f clkin 238/255 fec scaling 20.826 41.652 83.305 166.61 333.22 666.44 ? ? ? ? ? ? 23.234 46.465 92.934 185.87 371.74 743.47 mhz input clock frequency (clkin) fec[2:0] = 100 (forward fec) infrqsel[2:0] = 001 infrqsel[2:0] = 010 infrqsel[2:0] = 011 infrqsel[2:0] = 100 infrqsel[2:0] = 101 infrqsel[2:0] = 110 f clkin 255/237 fec scaling minimum input frequency is in the 155 mhz range n/a n/a n/a 144.52 289.05 578.11 n/a n/a n/a ? ? ? n/a n/a n/a 161.23 322.46 644.92 mhz input clock frequency (clkin) fec[2:0] = 101 (reverse fec) infrqsel[2:0] = 001 infrqsel[2:0] = 010 infrqsel[2:0] = 011 infrqsel[2:0] = 100 infrqsel[2:0] = 101 infrqsel[2:0] = 110 f clkin 237/255 fec scaling minimum input frequency is in the 155 mhz range n/a n/a n/a 167.31 334.62 669.25 n/a n/a n/a ? ? ? n/a n/a n/a 186.66 373.31 746.61 mhz note: the si5321 provides a 1/32x, 1/16x, 1/8x , 1/4x, 1/2x, 1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x clock multiplication function with an option for additional frequency scaling by a factor of 255/238, 238/255, 255/237, 23 7/255, 66/64, or 64/66 for fec rate conversion.
si5321-xc3 8 rev. 2.4 input clock frequency (clkin) fec[2:0] = 110 (reverse fec) infrqsel[2:0] = 001 infrqsel[2:0] = 010 infrqsel[2:0] = 011 infrqsel[2:0] = 100 infrqsel[2:0] = 101 infrqsel[2:0] = 110 f clkin 66/64 fec scaling minimum input frequency is in the 155 mhz range n/a n/a n/a 150.79 301.58 603.16 n/a n/a n/a ? ? ? n/a n/a n/a 168.22 336.44 672.88 mhz input clock frequency (clkin) fec[2:0] = 111 (reverse fec) infrqsel[2:0] = 001 infrqsel[2:0] = 010 infrqsel[2:0] = 011 infrqsel[2:0] = 100 infrqsel[2:0] = 101 infrqsel[2:0] = 110 f clkin 64/66 fec scaling minimum input frequency is in the 155 mhz range n/a n/a n/a 160.36 320.72 641.46 n/a n/a n/a ? ? ? n/a n/a n/a 178.90 357.80 715.59 mhz input clock rise time (clkin) t r figure 2 ? ? 11 ns input clock fall time (clkin) t f figure 2 ? ? 11 ns input clock duty cycle c duty_in 40 50 60 % clkout frequency range frqsel[2:0] = 001 frqsel[2:0] = 000 frqsel[2:0] = 100 frqsel[2:0] = 010 frqsel[2:0] = 101 frqsel[2:0] = 011 frqsel[2:0] = 110 frqsel[2:0] = 111 f o_19 f o_39 f o_78 f o_155 f o_311 f o_622 f o_1250 f o_2500 19.436 38.872 77.744 155.48 310.97 621.95 1243.9 2487.8 ? ? ? ? ? ? ? ? 21.685 43.369 86.738 173.48 346.95 693.90 1387.8 2775.6 mhz clkout rise time t r figure 2; single-ended; after 3 cm of 50 fr4 stripline ?190220ps clkout fall time t f figure 2; single-ended; after 3 cm of 50 fr4 stripline ?185205ps output clock duty cycle c duty_out differential: (clkout+) ? (clkout?) 48 ? 52 % rstn/cal pulse width t rstn 20 ? ? ns table 3. ac characteristics (continued) (v dd33 =3.3v 5%, t a = ?40 to 85 c) parameter symbol test co ndition min typ max unit note: the si5321 provides a 1/32x, 1/16x, 1/8x , 1/4x, 1/2x, 1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x clock multiplication function with an option for additional frequency scaling by a factor of 255/238, 238/255, 255/237, 23 7/255, 66/64, or 64/66 for fec rate conversion.
si5321-xc3 rev. 2.4 9 transitionless period required on clkin for dete cting a los condition. infrqsel[2:0] = 001 infrqsel[2:0] = 010 infrqsel[2:0] = 011 infrqsel[2:0] = 100 infrqsel[2:0] = 101 infrqsel[2:0] = 110 t los figure 3 24 / fo_622 16 / fo_622 12 / fo_622 10 / fo_622 9 / fo_622 8 / fo_622 ? ? ? ? ? ? 32 / fo_622 32 / fo_622 32 / fo_622 32 / fo_622 32 / fo_622 32 / fo_622 s recovery time for clearing an los condition valtime = 0 valtime = 1 t val measured from when a valid reference clock is applied until the los flag clears 1.6 90 ? ? 3.2 220 ms table 3. ac characteristics (continued) (v dd33 =3.3v 5%, t a = ?40 to 85 c) parameter symbol test co ndition min typ max unit note: the si5321 provides a 1/32x, 1/16x, 1/8x , 1/4x, 1/2x, 1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x clock multiplication function with an option for additional frequency scaling by a factor of 255/238, 238/255, 255/237, 23 7/255, 66/64, or 64/66 for fec rate conversion.
si5321-xc3 10 rev. 2.4 table 4. ac characteristics (pll performance characteristics) (v dd33 =3.3v 5%, ta=?40 to 85c) parameter symbol test condition min typ max unit wander/jitter at 800 hz bandwidth (bwsel[1:0] = 10 and bwboost = 0) jitter tolerance (see figure 6) j tol(pp) f=8hz 1000 ? ?ns f=80hz 100 ? ?ns f=800hz 10 ? ?ns clkout rms jitter generation fec[2:0] = 000 j gen(rms) 12 khz to 20 mhz ? 0.9 1.2 ps 50 khz to 80 mhz ? 0.27 0.35 ps clkout rms jitter generation fec[2:0] = 001, 010, 100, 101, 110, 111 j gen(rms) 12 khz to 20 mhz ? 0.9 1.2 ps 50 khz to 80 mhz ? 0.27 0.35 ps clkout peak-peak jitter generation fec[2:0] = 000 j gen(pp) 12 khz to 20 mhz ? 7.6 11 ps 50 khz to 80 mhz ? 3.6 10.0 ps clkout peak-peak jitter generation fec[2:0] = 001, 010, 100, 101, 110, 111 j gen(pp) 12 khz to 20 mhz ? 6.7 9.2 ps 50 khz to 80 mhz ? 3.0 10.0 ps jitter transfer bandwidth (see figure 5) f bw bw = 800 hz ? 800 ? hz wander/jitter transfer peaking j p < 800 hz ? 0.0 0.05 db wander/jitter at 1600 hz bandwidth (bwsel[1:0] = 10 and bwboost = 1) jitter tolerance (see figure 6) f = 16 hz 500 ? ? ns f=160hz 50 ? ? ns f = 1600 hz 5 ? ? ns clkout rms jitter generation fec[2:0] = 000 j gen(rms) 12 khz to 20 mhz ? .80 1.0 ps 50 khz to 80 mhz ? .25 .30 ps clkout peak-peak jitter generation fec[2:0] = 000 j gen(pp) 12 khz to 20 mhz ? 6.4 10.0 ps 50 khz to 80 mhz ? 3.0 5.0 ps jitter transfer bandwidth (see figure 5) f bw bw = 1600 hz ? 1600 ? hz wander/jitter transfer peaking j p < 1600 hz ? 0.0 0.05 db wander/jitter at 1600 hz bandwidth (bwsel[1:0] = 01 and bwboost = 0) jitter tolerance (see figure 8) j tol(pp) f = 16 hz 1000 ? ? ns f = 160 hz 100 ? ? ns f = 1600 hz 10 ? ? ns notes: 1. higher pll bandwidth settings provide smaller clock output wander with temperature gradient. 2. for reliable device operation, temperature gradients should be limited to 10 c/min. 3. telcordia gr-1244-core requirements specify maximum p hase transient slope during clock rearrangement in terms of nanoseconds per millisecond. the equivalent ps/ s unit is used here since the maximum phase transient magnitude for the si5321 (tpt_mtie) never reaches one nanosecond.
si5321-xc3 rev. 2.4 11 clkout rms jitter generation fec[2:0] = 000 j gen(rms) 12 khz to 20 mhz ? 0.8 1.2 ps 50 khz to 80 mhz ? 0.27 0.35 ps clkout rms jitter generation fec[2:0] = 001, 010, 100, 101, 110, 111 j gen(rms) 12 khz to 20 mhz, ? 0.9 1.2 ps 50 khz to 80 mhz, ? 0.27 0.35 ps clkout peak-peak jitter generation fec[2:0] = 000 j gen(pp) 12 khz to 20 mhz, ? 6.7 10.0 ps 50 khz to 80 mhz, ? 3.0 5.0 ps clkout peak-peak jitter generation fec[2:0] = 001, 010, 100, 101, 110, 111 j gen(pp) 12 khz to 20 mhz, ? 6.5 10.0 ps 50 khz to 80 mhz, ? 3.0 5.0 ps jitter transfer bandwidth (see figure 5) f bw bw = 1600 hz ? 1600 ? hz wander/jitter transfer peaking j p < 1600 hz ? 0.0 0.1 db wander/jitter at 3200 hz bandwidth (bwsel[1:0] = 01 and bwboost = 1) jitter tolerance (see figure 7) f = 32 hz 500 ? ? ns f=320hz 50 ? ? ns f = 3200 hz 5 ? ? ns clkout rms jitter generation fec[2:0] = 000 j gen(rms) 12 khz to 20 mhz, ? 0.8 1.0 ps 50 khz to 80 mhz, ? 0.25 0.3 ps clkout peak-peak jitter generation fec[2:0] = 000 j gen(pp) 12 khz to 20 mhz, ? 6.1 10.0 ps 50 khz to 80 mhz, ? 3.0 5.0 ps jitter transfer bandwidth (see figure 5) f bw bw = 3200 hz ? 3200 ? hz wander/jitter transfer peaking j p < 3200 hz ? 0.05 0.1 db wander/jitter at 3200 hz bandwidth (bwsel[1:0] = 00 and bwboost = 0) jitter tolerance (see figure 6) j tol(pp) f=32hz 1000 ? ?ns f=320hz 100 ? ?ns f = 3200 hz 10 ? ?ns clkout rms jitter generation fec[2:0] = 000 j gen(rms) 12 khz to 20 mhz ? 0.9 1.1 ps 50 khz to 80 mhz ? 0.3 0.4 ps clkout rms jitter generation fec[2:0] = 001, 010, 100,101, 110, 111 j gen(rms) 12 khz to 20 mhz ? 0.85 1.1 ps 50 khz to 80 mhz ? 0.3 0.45 ps table 4. ac characteristics (pll performance characteristics) (continued) (v dd33 =3.3v 5%, ta=?40 to 85c) parameter symbol test condition min typ max unit notes: 1. higher pll bandwidth settings provide smaller clock output wander with temperature gradient. 2. for reliable device operation, temperature gradients should be limited to 10 c/min. 3. telcordia gr-1244-core requirements specify maximum p hase transient slope during clock rearrangement in terms of nanoseconds per millisecond. the equivalent ps/ s unit is used here since the maximum phase transient magnitude for the si5321 (tpt_mtie) never reaches one nanosecond.
si5321-xc3 12 rev. 2.4 clkout peak-peak jitter generation fec[2:0] = 000 j gen(pp) 12 khz to 20 mhz ? 7.1 10.0 ps 50 khz to 80 mhz ? 3.2 5.0 ps clkout peak-peak jitter generation fec[2:0] = 001, 010, 100,101, 110, 111 j gen(pp) 12 khz to 20 mhz ? 6.6 11.0 ps 50 khz to 80 mhz ? 3.2 5.5 ps jitter transfer bandwidth (see figure 5) f bw bw = 3200 hz ? 3200 ?hz wander/jitter transfer peaking j p < 3200 hz ? 0.05 0.1 db wander/jitter at 6400 hz bandwidth (bwsel[1:0] = 00 and bwboost = 1) jitter tolerance (see figure 6) f = 64 hz 500 ? ? ns f=640hz 50 ? ? ns f = 6400 hz 5 ? ? ns clkout rms jitter generation fec[2:0] = 000 j gen(rms) 12 khz to 20 mhz ? 0.75 0.95 ps 50 khz to 80 mhz ? 0.27 0.35 ps clkout peak-peak jitter generation fec[2:0] = 000 j gen(pp) 12 khz to 20 mhz ? 6.1 10.0 ps 50 khz to 80 mhz ? 3.1 5.0 ps jitter transfer bandwidth (see figure 5) f bw bw = 6400 hz ? 6400 ? hz wander/jitter transfer peaking j p < 6400 hz ? 0.05 0.1 db wander/jitter at 6400 hz bandwidth (bwsel[1:0] = 11 and bwboost = 0) jitter tolerance (see figure 6) j tol(pp) f=64hz 1000 ? ?ns f=640hz 100 ? ?ns f = 6400 hz 10 ? ?ns clkout rms jitter generation fec[2:0] = 000 j gen(rms) 12 khz to 20 mhz ? 1.0 1.3 ps 50 khz to 80 mhz ? 0.4 .55 ps clkout rms jitter generation fec[2:0] = 001, 010, 100,101, 110, 111 j gen(rms) 12 khz to 20 mhz ? 1.0 1.5 ps 50 khz to 80 mhz ? .45 0.7 ps clkout peak-peak jitter generation fec[2:0] = 000 j gen(pp) 12 khz to 20 mhz ? 9.3 13.0 ps 50 khz to 80 mhz ? 4.1 6.0 ps clkout peak-peak jitter generation fec[2:0] = 001, 010, 100,101, 110, 111 j gen(pp) 12 khz to 20 mhz ? 8.0 20.0 ps 50 khz to 80 mhz ? 4.0 7.5 ps jitter transfer bandwidth (see figure 5) f bw bw = 6400 hz ? 6400 ?hz wander/jitter transfer peaking j p < 6400 hz ? 0.05 0.1 db wander/jitter at 12800 hz bandwidth (bwsel[1:0] = 11 and bwboost = 1) table 4. ac characteristics (pll performance characteristics) (continued) (v dd33 =3.3v 5%, ta=?40 to 85c) parameter symbol test condition min typ max unit notes: 1. higher pll bandwidth settings provide smaller clock output wander with temperature gradient. 2. for reliable device operation, temperature gradients should be limited to 10 c/min. 3. telcordia gr-1244-core requirements specify maximum p hase transient slope during clock rearrangement in terms of nanoseconds per millisecond. the equivalent ps/ s unit is used here since the maximum phase transient magnitude for the si5321 (tpt_mtie) never reaches one nanosecond.
si5321-xc3 rev. 2.4 13 jitter tolerance (see figure 6) f = 128 hz 500 ? ? ns f = 1280 hz 50 ? ? ns f = 12800 hz 5 ? ? ns clkout rms jitter generation fec[2:0] = 000 j gen(rms) 12 khz to 20 mhz ? .85 1.2 ps 50 khz to 80 mhz ? .35 .55 ps clkout peak-peak jitter generation fec[2:0] = 000 j gen(pp) 12 khz to 20 mhz ? 6.8 11.0 ps 50 khz to 80 mhz ? 3.4 5.5 ps jitter transfer bandwidth (see figure 5) f bw bw = 12,800 hz ? 12800 ? hz wander/jitter transfer peaking j p < 12,800 hz ? 0.05 .1 db acquisition time t aq rstn/cal high to cal_actv low, with valid clock input and valtime = 0 ? 300 350 ms clock output wander with temperature gradient 1,2 c co_tg stable input clock; temperature gradient <10 c/min; 800 hz loop bw ? ? 45 ps/ c/ min initial frequency accuracy in digital hold mode (first 100 ms with voltage and temperature held constant) c dh_fa stable input clock selected until entering digital hold ? ? 5.5 ppm clock output frequency accuracy over temperature in digital hold mode c dh_t constant supply voltage ? 17.2 40 ppm / c clock output frequency accuracy over supply voltage in digital hold mode c dh_v33 constant temperature ? ? 600 ppm /v clock output phase step 3 (see figure 7) t pt_mtie when hitlessly recovering from digital hold mode ?200 0 200 ps clock output phase step slope 3 (see figure 7) bwsel[1:0] = 11, bwboost = 0 bwsel[1:0] = 00, bwboost = 0 bwsel[1:0] = 01, bwboost = 0 bwsel[1:0] = 10, bwboost = 0 m pt when hitlessly recovering from digital hold mode 6400 hz, no scaling 3200 hz, no scaling 1600 hz, no scaling 800 hz, no scaling ? ? ? ? ? ? ? ? 10 5 2.5 1.25 ps/ s table 4. ac characteristics (pll performance characteristics) (continued) (v dd33 =3.3v 5%, ta=?40 to 85c) parameter symbol test condition min typ max unit notes: 1. higher pll bandwidth settings provide smaller clock output wander with temperature gradient. 2. for reliable device operation, temperature gradients should be limited to 10 c/min. 3. telcordia gr-1244-core requirements specify maximum p hase transient slope during clock rearrangement in terms of nanoseconds per millisecond. the equivalent ps/ s unit is used here since the maximum phase transient magnitude for the si5321 (tpt_mtie) never reaches one nanosecond.
si5321-xc3 14 rev. 2.4 figure 4. typical si5321 phase noise (clkin = 155.52 mhz, clkout = 622.08 mhz, and loop bw = 800 hz) table 5. absolute maximum ratings parameter symbol value unit 3.3 v dc supply voltage v dd33 ?0.5 to 3.6 v lvttl input voltage v dig ?0.3 to (v dd33 + 0.3) v maximum current any output pin 50 ma operating junction temperature t jct ?55 to 150 c storage temperature range t stg ?55 to 150 c esd hbm tolerance (100 pf, 1.5 k )1.0kv note: permanent device damage may occur if the absolute maximum ratings are exceeded. functi onal operation should be restricted to the conditions as specif ied in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 6. thermal characteristics parameter symbol test condition value unit thermal resistance junction to ambient ? ja still air 46 c/w 10 1 -160 -140 -120 -100 -80 -60 -40 -20 0 10 6 10 5 10 4 10 3 10 2 10 7 10 8 offset frequency phase noise (dbc/hz)
si5321-xc3 rev. 2.4 15 2. typical application schematic (3.3 v supply) 10 k 1% los clkin+ valtime clkin? input clock source loss of signal (los) digital hold active los validation time dh_actv pwrdn/cal fec[2:0] bwsel[1:0] pll bandwidth select fec scaling select powerdown control cal_actv frqsel[2:0] clkout+ clkout? clock output clock output frequency select calibration active status output rext vsel33 vdd25 vdd33 gnd 0.1 f 3.3 v supply 2200 pf 22 pf si5321 infrqsel[2:0] input clock frequency select 33 f bwboost pll bandwidth multiplier fxddelay fixed delay mode control ferrite bead 0.1 f 100 0.1 f 0.1 f 0.1 f
si5321-xc3 16 rev. 2.4 3. functional description the si5321 is a high-performance precision clock multiplication and clock generation device. this device accepts a clock input in the 19, 39, 78, 155, 311, or 622 mhz range, attenuates si gnificant amounts of jitter, and multiplies the input clock frequency to generate a clock output in the 19, 39, 78, 155, 311, 622, 1250, or 2500 mhz range. additional forward or reverse clock rate scaling by a factor of 255/238, 255/237, or 66/64 is provided. this allows systems to easily provide clocks that are scaled for forward error correction (fec) rates. the 255/238 and 255/237 factors support the itu-t g.709 requirements for optical transport unit (otu) oc- 48 and oc-192 rates. the 66/64 factor allows conversion between xsbi and 10 gbe base r rates. typical applications for the si5321 in sonet/sdh systems are generation and/or cleaning of 19.44, 38.88, 77.76, 155.52, 311.04, 622.08, 1244.16, or 2488.32 mhz clocks from 19.44, 38.88, 77.76, 155.52, 311.04, or 622.08 mhz clock sources. the si5321 employs silicon laboratories dspll ? technology to provide excellent jitter performance while minimizing the external component count and maximizing flexibility and ea se of use. the si5321 dspll phase locks to the input clock signal, attenuates jitter, and multiplies the clock frequency to generate the device?s sonet/sdh-compliant clock output. the dspll loop bandwidth is user-selectable, allowing si5321 jitter performance optimization for different applications. the si5321 can produce a clock output with jitter generation as low as 0.3 ps rms (see table 4 on page 10), making the device an ideal solution for clock multiplication in sonet/sdh (including oc-48, oc-192, and oc768), gigabit ethernet, and 10 gbe systems. the si5321 monitors the clock input signal for loss-of- signal and provides a loss-of-signal (los) alarm when it detects missing pulses. the si5321 provides a digital hold capability that allows the device to continue generation of a stable output clock when the input reference is lost. 3.1. dspll? the si5321?s phase-locked loop (pll) uses silicon laboratories' dspll technology to eliminate jitter, noise, and the need for external loop filter components found in traditional pll implementations. this is achieved by using a digital signal processing (dsp) algorithm to replace the loop filter commonly found in analog pll designs. this algorithm processes the phase detector error term and generates a digital control value to adjust the frequency of the voltage- controlled oscillato r (vco). the technology produces clocks with less jitter than is generated using traditional methods. see figure 4 for an example phase noise plot. in addition, because external loop filter components are not required, sensitive noise entry points are eliminated, thus making the dspll less susceptible to board-level noise sources. this digital technology also provides highly-stable and consistent operation over all process, temperature, and voltage variations. the benefits are smaller, lower power, cleaner , reliable, and easy-to-use clock circuits. 3.1.1. selectable loop filter bandwidth the digital characteristics of the dspll loop filter allow control of the loop filter parameters without the need to change external components. the si5321 provides the user with up to eight user-selectable loop bandwidth settings for different system requirements. the base loop bandwidth is selected using the bwsel[1:0] pins along with bwboost = 0 pins. when the bwboost is driven high, the bandwidth selected on the bwsel[1:0] pins is doubled. (see table 7.) when the bwboost pin is as serted, the si5321 shows improved jitter generation performance. the bwboost function is defined only when hitless recovery and fec scaling are disabled. therefore, when bwboost is high, the user must also drive fxddelay high and fec[1:0] to 000 for proper operation. 3.2. clock input and output rate selection the si5321 provides a 1/32x, 1/16x, 1/8x, 1/4x, 1/2x, 1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x clock frequency multiplication function with an option for additional frequency scaling by a factor of 255/238, 238/255, 255/ 237, 237/255, 66/64, or 64/66 for fec rate compatibility. output rates vary in accordan ce with the input clock rate. the multiplication factor is configured by selecting the input and output clock frequency ranges for the device. the si5321 accepts an input clock in the 19, 38, 77, 155, 311, or 622 mhz frequency range. the input frequency range is selected using the infrqsel[2:0] pins. the infrqsel[2:0] settings and associated output clock rates are listed in table 8. the si5321?s dspll phase locks to the clock input signal to generate an internal vco frequency that is a multiple of the input clock frequency. the internal vco frequency is divided down to produce a clock output in the 19, 39, 78, 155, 311, 622, 1250, or 2500 mhz frequency range. the clock output range is selected using the frequency select (frqsel[2:0]) pins. the frqsel[2:0] settings and associated output clock rates are given in table 9.
si5321-xc3 rev. 2.4 17 the si5321 clock input frequencies are variable within the range specified in table 3 on page 7. the output rates are scaled accordingly. if a 19.44 mhz input clock is used, the clock output frequency is 19.44, 38.88, 77.76, 155.52 mhz, etc. 3.2.1. fec rate conversion the si5321 provides a 1/32x , 1/16x, 1/8x, 1/4x, 1/2x, 1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x clock frequency multiplication function wit h an option for additional forward or reverse frequency scaling by a factor of 255/ 238 (15/14), 255/237 (85/79), or 66/64 (33/32) for fec rate conversion applications. the 255/237 and the 66/ 64 rate conversions requires th e input clock rate to be in the 155 mhz or higher ranges. the multiplication factor is configured by selectin g the input and output clock frequency ranges for the device. the additional frequency scaling for fec rate conversion is selected using the fec[2:0] control inputs. for example, a 622.08 mhz output clock (a non-fec rate) can be generated from a 19.44 mhz input clock (a non-fec rate) by setting infrqsel[2:0] = 001 (19.44 mhz range), setting frqsel[2:0] = 011 (32x multiplication) and setting fec[2:0] = 000 (no fec scaling). a 666.51 mhz output clock (an fec rate) can be generated from a 19.44 mhz input clock (a non-fec rate) by setting infrqsel[2:0] = 001 (19.44 mhz range), setting frqsel[2:0 ] = 011 (32x multiplication) table 7. loop bandwidth and fec settings external inputs effective fec conversion rate effective pll bandwidth (hz) bwboost bwsel [1:0] fec [2:0] 0 0 0 0 0 0 0 0 00 00 00 00 00 00 00 00 000 001 010 011 100 101 110 111 1/1 255/238 238/255 reserved 255/237 237/255 66/64 64/66 3200 3200 3200 ? 3200 3200 3200 3200 0 0 0 0 0 0 0 0 10 10 10 10 10 10 10 10 000 001 010 011 100 101 110 111 1/1 255/238 238/255 reserved 255/237 237/255 66/64 64/66 800 800 800 ? 800 800 800 800 0 0 0 0 0 0 0 0 11 11 11 11 11 11 11 11 000 001 010 011 100 101 110 111 1/1 255/238 238/255 reserved 255/237 237/255 66/64 64/66 6400 6400 6400 ? 6400 6400 6400 6400 1 1 1 1 00 10 11 01 0xx 0xx 0xx 0xx 1/1 1/1 1/1 1/1 6400 1600 12800 3200 0 0 0 0 0 0 0 0 01 01 01 01 01 01 01 01 000 001 010 011 100 101 110 111 1/1 255/238 238/255 reserved 255/237 237/255 66/64 64/66 1600 1600 1600 ? 1600 1600 1600 1600 table 8. nominal clock input frequencies input clock frequency range infrqsel2 infrq sel1 infrqsel0 reserved111 622mhz110 311mhz101 155mhz 100 77mhz 011 38mhz 010 19mhz 001 reserved000 table 9. nominal clock output frequencies output clock frequency range frqsel2 frqsel1 frqsel0 2,488.32 mhz 1 1 1 1244.16 mhz 1 1 0 622.08 mhz 0 1 1 311.04 mhz 1 0 1 155.52 mhz 0 1 0 77.76 mhz 1 0 0 38.88 mhz 0 0 0 19.44 mhz 0 0 1
si5321-xc3 18 rev. 2.4 and setting fec[2:0] = 001 (255/238 fec scaling). finally, a 622.08 mhz output clock (a non-fec rate) can be generated from a 20.83 mhz input clock (an fec rate) by setting infrqsel[2:0] = 001 (19.44 mhz range), setting frqsel[2:0 ] = 011 (32x multiplication) and setting fec[2:0] = 010 (238/255 fec scaling). 3.3. pll performance the si5321 pll provides extremely low jitter generation, high jitter tolerance, and a well-controlled jitter transfer function with low peaking and a high degree of jitter attenuation. 3.3.1. jitter generation jitter generation is defined as the amount of jitter produced at the output of the device with a jitter free input clock. generated jitter arises from sources within the vco and other pll components. jitter generation is a function of the pll bandwidth setting. higher loop bandwidth settings may result in lower jitter generation but may also result in less attenuation of jitter than might be present on the input clock signal. 3.3.2. jitter transfer jitter transfer is defined as th e ratio of output signal jitter to input signal jitter for a specified jitter frequency. the jitter transfer characteristic determines the amount of input clock jitter that passes to the outputs. the dspll technology used in the si5321 provides tightly- controlled jitter transfer curves because the pll gain parameters are determined by digital circuits that do not vary over supply voltage, process, and temperature. in a system application, a we ll-controlled transfer curve minimizes the output clock jitter variation from board to board and provides more cons istent system level jitter performance. the jitter transfer characteristic is a function of the bwsel[1:0] setting. lower bandwidth settings result in more jitter attenuation of the incoming clock but may result in higher jitter generation. table 4 on page 10 gives the 3 db bandwidth and peaking values for specified bwsel settings. figure 5 shows the jitter transfer curve mask. . figure 5. pll jitter transfer mask/template 3.3.3. jitter tolerance jitter tolerance for the si5321 is defined as the maximum peak-to-peak sinusoidal jitter that can be present on the incoming clock. the tolerance is a function of the jitter frequency because tolerance improves for lower in put jitter frequency. figure 6. jitter tolerance mask/template 3.4. loss-of-signal alarm the si5321 has loss-of-signal (los) circuitry that constantly monitors the clkin input clock for missing pulses. the los circuitry sets a los output alarm signal when missing pulses are detected. the los circuitry operates as follows. regardless of the selected input clock frequency range, the los circuitry divides down the input clock into the 19 mhz range. the los circuitry then over-samples this divided down input clock to search for extended periods of time without input clock transitions. if the los circuitry detects four consecutive sa mples of the divided down input clock that are the same state (i.e., 1111 or 0000), a los condition is declared; the si5321 goes into digital hold mode, and the los output alarm signal is set high. the los sampling circuitry runs at a frequency of f o_78 , where f o_78 is the output clock frequency when the frqsel[2:0] pins are set to 100. figure 3 on page 5 and table 3 on page 7 list the minimum and maximum transitionless time periods required for declaring a los on the input clock (t los ). once the los alarm is asserted, it is held high until the input clock is validated over a time period designated by the valtime pin. when valtime is low, the validation time period is about 1 ms. when valtime is high, the validation time period is about 100 ms. if another los condition is detected on the input clock during the validation time (i.e., if another set of 1111 or 0000 samples are detected), the los alarm remains asserted, and the validation time starts over. when the los alarm is finally releas ed, the si5321 exits digital hold mode and locks to the input clock. the los alarm jitter transfer 0 db f bw f jitter peaking ?20 db/dec. jitter out jitter in (s) j p input jitter amplitude 10 ns f bw ?20 db/dec. f jitter in excessive input jitter range
si5321-xc3 rev. 2.4 19 is automatically set high at power-on and at every low- to-high transition of the rstn/cal pin. in these cases, the si5321 undergoes a self-calibration before releasing the los alarm and locking to the input clock. the si5321 also provides an output indicating the digital hold status of the device, dh_actv. the si5321 only enters the digital hold mode upon the loss of the input clock. when this occurs, the los alarm will also be active. therefore, applications that require monitoring of the status of the si5321 need only monitor the cal_actv and either the los or dh_actv outputs to know the state of the device. 3.5. digital hold of the pll when no valid input clock is available, the si5321 digitally holds the internal os cillator to its last frequency value. this provides a stable clock to the system until an input clock is valid again. this clock maintains stable operation in the presence of constant voltage and temperature. the frequency accuracy specifications for digital hold mode are given in table 4 on page 10. 3.6. hitless recover y from digital hold when the si5321 device is locked to a valid input clock, a loss of the input clock switches the device to digital hold mode. when the input clock signal returns, the device performs a hitless transition from digital hold mode back to the selected input clock. that is, the device executes ?phase build-out? to absorb the phase difference between the internal vco clock operating in digital hold mode and the new/returned input clock. the maximum phase step seen at the clock output during this transition, and the maximum slope of this step, is specified in table 4 on page 10. asserting the fixed delay (fxddelay) pin disables this feature and the output clock phase and frequency locks with a known phase relationship to the input clock. consequently, an abrupt phase change on the input clock propagates through the device, and the output slews at the loop bandwidth until the phase relationship is restored. figure 7. recovery from digital hold 3.7. reset the si5321 provides a reset/calibration pin (rstn/ cal) that resets the device and disables all of the device outputs. when the rstn/cal pin is driven low, the internal circuitry enters reset mode, and all lvttl outputs are forced into a high-impedance state. also, the clkout+ and clkout? pins are connected to v dd25 through 100 on-chip resistors. this feature is useful for applications that employ redundant clock sources and for in-circuit test applications. a low-to-high transition on rstn/cal initia lizes all digital logic to a known condition and initiate s self-calibration of the dspll. upon completion of self-calibration, the dspll begins to lock to the clock input signal. 3.8. pll self-calibration the si5321 achieves optimal jitter performance by using self-calibration circuitry to set the vco center frequency and loop gain parameters within the dspll. internal circuitry generates self calibration automatically on powerup or after a loss-of-power condition. self- calibration can also be manu ally initiated by a low-to- high transition on the rstn/cal input. a self-calibration sh ould be initiated after changing the state of the fec[2:0] inputs . whether manually initiated or automatically initiated at powerup, the self-calibration process requires the presence of a valid input clock. if the self-calibration is initiated without a valid input clock, the device waits for a valid input clock before executing the self-calibration. the si5321 does not provide an output clock while waiting for a valid input clock or while executing its self-calibration. when the input clock is validated, the calibration procedure executes to completion; the device locks to the input clock, and the output clock turns on. subsequent losses of the input clock do not requ ire self-calibration. if the input clock is lost following self-calibration, the device recovery from digital hold m pt t pt_mtie
si5321-xc3 20 rev. 2.4 enters digital hold mode with the output clock frequency held to its last value be fore the los condition was detected. when the input clock returns and is validated, the device exits digital hold mode by re-locking to the input clock without executing another self-calibration. 3.9. bias generation circuitry the si5321 makes use of an external resistor to set internal bias currents. the external resistor allows precise generation of bias currents, which significantly reduces power consumption and variation as compared to traditional implementations using an internal resistor. the bias generation circuitry requires a 10 k (1%) resistor connected between rext and gnd. 3.10. differential input circuitry the si5321 provides a differential input for the clock input, clkin. this input is in ternally-biased to a voltage of v icm (see table 2 on page 6) and may be driven by a differential or single-ended driver circuit. for transmission line termination, the termination resistor is connected externally as shown. 3.11. differential output circuitry the si5321 utilizes a curr ent mode logic (cml) architecture to drive the differential clock output, clkout. for single-ended output operation simply connect to either clkout+ or clkout? and leave the unused signal unconnected. 3.12. power supply connections the si5321 incorporates an on-chip voltage regulator to power the device from a 3.3 v supply. the voltage regulator requires an external compensation circuit of one resistor and on e capacitor to ensure stability over all operating conditions. internally, the si5321 v dd33 pins are connected to the on-chip voltage regulator input and to the device?s lvttl i/o circuitry. the v dd25 pins supply power to the core dspll circuitry and are used for connection of the external compensation circuit. the regulator?s compensation circuit is a resistor and a capacitor in series between the v dd25 node and ground. typically, the resistor is incorporated into the capacitor?s equivalent series resistance (esr). the target rc time constant for this combination is 15 to 50 s. the capacitor used in the si5321 evaluation board is a 33 f tantalum capacitor with an esr of 0.8 . this gives an rc time constant of 26.4 s. the venkel part number, ta6r3tcr336kbr, is an example of a capacitor that meets these specifications. (s ee "2. typical application schematic (3.3 v supply)" on page 15.) to get optimal performance from the si5321 device, the power supply noise spectrum must comply with the plot in figure 8. this plot shows the power supply noise tolerance mask for the si5321. the customer should provide a 3.3 v supply that does not have noise density in excess of the amount shown in the diagram. however, the diagram cannot be used as spur criteria for a power supply that contains single tone noise. figure 8. power supply noise tolerance mask f v n ( v / hz ) 2100 42 10 khz 500 khz 100 mhz
si5321-xc3 rev. 2.4 21 3.13. design and layout guidelines precision clock circuits are susceptible to board noise and emi. to take precautions against unacceptable levels of board noise and emi affecting performance of the si5321, consider the following: ? power the device from 3.3 v since the internal regulator provides >40 db of isolation to the v dd25 pins (which power the pll circuitry). ? when powering the device from 3.3 v, use an isolated, local plane to connect the v dd25 pins. avoid running signal traces over or below this plane without a ground plane in between. ? route all i/o traces between ground planes as much as possible. ? maintain an input clock amplitude in the 200 mv pp to 500 mv pp differential range. ? excessive high-frequency harmonics of the input clock should be minimized. the use of filters on the input clock signal can be used to remove high- frequency harmonics.
si5321-xc3 22 rev. 2.4 4. pin descriptions: si5321 figure 9. si5321 pin configuration (bottom view) bottom view a b c d e f g h 1 7 8 65432 rstn/cal valtime frqsel[0] clkout+ clkout? frqsel[1] infrqsel[1] gnd gnd gnd gnd gnd gnd gnd infrqsel[0] gnd vdd25 vdd25 vdd25 vdd25 vdd25 los clkin? gnd vdd33 vdd33 vdd33 vdd25 vdd25 cal_actv clkin+ bwboost vdd33 vdd33 vdd33 vdd25 vdd25 dh_actv bwsel[1] vsel33 gnd gnd gnd gnd gnd rsvd_gnd bwsel[0] fec[2] frqsel[2] fxddelay rsvd_nc rsvd_gnd rsvd_gnd rsvd_nc fec[1] fec[0] rsvd_nc rsvd_nc rsvd_nc rsvd_nc rsvd_nc rext infrqsel[2]
si5321-xc3 rev. 2.4 23 figure 10. si5321 pin configuration (transparent top view) top view a b c d e f g h rstn/cal valtime frqsel[0] clkout+ clkout? frqsel[1] infrqsel[1] gnd gnd gnd gnd gnd gnd gnd infrqsel[0] gnd vdd25 vdd25 vdd25 vdd25 vdd25 los gnd vdd33 vdd33 vdd33 vdd25 vdd25 cal_actv clkin+ bwboost vdd33 vdd33 vdd33 vdd25 vdd25 dh_actv bwsel[1] vsel33 gnd gnd gnd gnd gnd rsvd_gnd bwsel[0] fec[2] frqsel[2] fxddelay rsvd_nc rsvd_gnd rsvd_gnd rsvd_nc fec[1] fec[0] rsvd_nc rsvd_nc rsvd_nc rsvd_nc rsvd_nc rext infrqsel[2] clkin? 178 6 5 4 3 2
si5321-xc3 24 rev. 2.4 table 10. si5321 pin descriptions pin # pin name i/o signal level description d1 e1 clkin+ clkin? i see table 2 system clock input. clock input to the dspll circuitry. the frequency of the clkin signal is multiplied by the dspll to gen- erate the clkout clock output. the input-to-output frequency multiplicat ion factor is set by selecting the clock input range and the clock output range. the frequency of the clkin clock input can be in the 19, 38, 77, 155, 311, or 622 mhz range (nominally 19.44, 38.88, 77.76, 155.52, 311.04, or 622.08 mhz) as indicated in table 3 on page 7. the clock input frequency is selected using the infrq- sel[2:0] pins. the clock output frequency is selected using the frqsel[1:0] pins. an additional scaling factor may be selected for fec operation using the fec[2:0] control pins. f1 g1 h1 infrqsel[0] infrqsel[1] infrqsel[2] i* lvttl* input frequency range select. pins(infrqsel[2:0]) select the frequency range for the input clock, clkin. (see table 3 on page 7.) 000 = reserved. 001 = 19 mhz range. 010 = 38 mhz range. 011 = 77 mhz range. 100 = 155 mhz range. 101 = 311 mhz range. 110 = 622 mhz range. 111 = reserved. h6 h7 clkout+ clkout? ocml differential clock output. high-frequency clock output. the frequency of the clkout output is a multiple of the frequency of the clkin input. the in put-to-output freq uency multipli- cation factor is set by selecting the clock input range and the clock output range . the frequency of the clkout clock output can be in the 19, 38, 77, 155, 311, 622, 1244 or 2488 mhz range as indicated in table 3 on page 7. the clo ck output frequency is selected using the frqsel[2:0] pins. the clock input frequency is selected using the infrq- sel[2:0] pins. an additio nal scaling factor may be selected for fec operatio n using the fec[2:0] con- trol pins. *note: the lvttl inputs on the si5321 device have an internal pulldown mechanism that causes the input to default to a logic low state if the input is not driven from an external source.
si5321-xc3 rev. 2.4 25 h5 h8 b3 frqsel[0] frqsel[1] frqsel[2] i* lvttl* clock output frequency range select. select the frequency range of the clock output, clk- out. (see table 3 on page 7.) 001 = 19 mhz frequency range. 000 = 39 mhz frequency range. 100 = 78 mhz frequency range. 010 = 155 mhz frequency range. 101 = 311 mhz frequency range. 011 = 622 mhz frequency range. 110 = 1.25 ghz frequency range. 111 = 2.5 ghz frequency range. a3 a2 b2 fec[0] fec[1] fec[2] i* lvttl* fec selection. enables or disables scaling of the input-to-output frequency multiplication factor for fec clock rate compatibility. the frequency of the clkout output is a multiple of the frequency of the clkin input. selecting the clock input range, the clock output range, and the fec scaling factor sets the input-to-output fre- quency multiplication factor. the clock output fre- quency is selected using the frqsel[2:0] pins. the clock input frequency is selected using the infrq- sel[2:0] pins. scaling factors of 255/238, 238/255, 255/237, 237/255, 66/64, or 64/66 may be selected for fec operation using the fec[2:0] control pins as indicated below. scaling factors of 255/237, 237/ 255, 66/64, or 64/66 require that the input clock rate be in the 155 mhz or higher range. 000 = no fec scaling. 001 = 255/238 fec scaling. 010 = 238/255 fec scaling. 011 = reserved. 100 = 255/237 fec scaling (155 mhz or higher input clock range required). 101 = 237/255 fec scaling (155 mhz or higher input clock range required). 110 = 66/64 fec scaling (155 mhz or higher input clock range required). 111 = 64/66 fec scaling (155 mhz or higher input clock range required). table 10. si5321 pin descriptions (continued) pin # pin name i/o signal level description *note: the lvttl inputs on the si5321 device have an internal pulldown mechanism that causes the input to default to a logic low state if the input is not driven from an external source.
si5321-xc3 26 rev. 2.4 b1 c1 bwsel[0] bwsel[1] i* lvttl* bandwidth select. bwsel[1:0] pins set the bandwidth of the loop filter within the dspll to 6400, 3200, 1600, or 800 hz as indicated below. 00 = 3200 hz 01 = 1600 hz 10 = 800 hz 11 = 6400 hz note: the loop filter bandwidth is twice the value indicated here when bwboost is set high. d2 bwboost i* lvttl* bandwidth boost. active high input to boos t the selected bandwidth 2x. when this pin is high, the loop filter bandwidth selected on bwsel[1:0] is doubled. when this pin is high, fxddelay must also be high and fec[2:0] must be 000. b4 fxddelay i* lvttl* fixed delay mode. set high to disable hitless recovery from digital hold mode. this configuration is useful in applications that require a known or constant input-to-output phase relationship. when this pin is high, hitless switching from digital hold mode back to a valid clock input is disabled. when switching from digital hold mode to a valid clock input with fxddelay high, the clock output changes as necessary to re-establish the initial/ default input-to-output phas e relationship that is established after powerup or reset. the rate of change is determined by the setting of bwsel[1:0]. when this pin is low, hitl ess switching from digital hold mode back to a valid clock input is enabled. when switching from digital hold mode to a valid clock input with fxddelay low, the device enables ?phase build out? to absorb the phase difference between the clock output and the clock input so that the phase change at the clock output is minimized. in this case, the input-to-output phase relationship following the transition out of digital hold mode is determined by the phase relationship at the time that switching occurs. note: fxddelay should remain at a static high or static low level during normal operation. transitions on this pin are allowed only when the rstn/cal pin is low. fxddelay must be set high when bwboost is set high. table 10. si5321 pin descriptions (continued) pin # pin name i/o signal level description *note: the lvttl inputs on the si5321 device have an internal pulldown mechanism that causes the input to default to a logic low state if the input is not driven from an external source.
si5321-xc3 rev. 2.4 27 h4 valtime i* lvttl* clock validation time for los. valtime sets the clock validation times for recovery from an los alarm condition. when valtime is high, the validation time is approximately 100 ms. when valtime is low, the validation time is approx- imately 2 ms. h3 rstn/cal i* lvttl* reset/calibrate. when low, all lvttl outputs are forced into a high impedance state, the dspll is forced out-of-lock, and the device control logic is reset. a low-to-high transition on rstn/cal initializes all digital logic to a known condition and initiates self- calibration of the dspll. at the completion of self- calibration, the dspll begins to lock to the selected clock input signal and begins to drive out the output clock signal onto the clkout pins. f8 los o lvttl loss-of-signal (los) alarm for clkin. active high output indi cates that the si5321 has detected missing pulses on the input clock signal. the los alarm is cleared after either 100 ms or 13 s of a valid clkin clock input depending on the set- ting of the valtime input. d8 dh_actv o lvttl digital hold mode active. active high output indicates that the dspll is in digital hold mode. digital hold mode locks the current state of the dspll and forces the dspll to continue generation of the output clock with no additional phase or frequency information from the input clock. e8 cal_actv o lvttl calibration mode active. this output is driven high during the dspll self-cal- ibration and the subsequent initial lock acquisition period. c2 vsel33 i* lvttl* select 3.3 v v dd supply. this is an enable pin for the internal regulator. to enable the regulator, connect this pin to the v dd33 pins. table 10. si5321 pin descriptions (continued) pin # pin name i/o signal level description *note: the lvttl inputs on the si5321 device have an internal pulldown mechanism that causes the input to default to a logic low state if the input is not driven from an external source.
si5321-xc3 28 rev. 2.4 d3?d5, e3?e5 v dd33 v dd supply 3.3 v supply. 3.3 v power is applied to the v dd33 pins. typical supply bypassing/decoupling for this configuration is indicated in the typical application diagram for 3.3 v supply operation. d6, d7, e6, e7, f3?f7 v dd25 v dd supply 2.5 v supply. these pins provide a means of connecting the compensation network for the on-chip regulator. c3?c7, e2, f2, g2?g8 gnd gnd supply ground. must be connected to system ground. minimize the ground path impedance for optimal performance of the device. h2 rext i analog external biasing resistor. used by on-chip circuitry to establish bias currents within the device. this pin must be connected to gnd through a 10 k (1%) resistor. a4?8, b5, b8 rsvd_nc lvttl reserved?no connect. this pin must be left unconnected for normal operation. b6, b7, c8 rsvd_gnd lvttl reserved?gnd. this pin must be tied to gnd for normal operation. table 10. si5321 pin descriptions (continued) pin # pin name i/o signal level description *note: the lvttl inputs on the si5321 device have an internal pulldown mechanism that causes the input to default to a logic low state if the input is not driven from an external source.
si5321-xc3 rev. 2.4 29 5. ordering guide part number package temperature range SI5321-G-XC3 63-ball cbga (prior revision) rohs-5 ?20 to 85 c si5321-h-xl3 63-ball pbga (current revision) rohs-5 ?20 to 85 c si5321-h-zl3 63-ball pbga (current revision) rohs-6 ?20 to 85 c
si5321-xc3 30 rev. 2.4 6. package outline figure 11 illustrates the package details for the si5321-xc3. table 11 lists the values for the dimensions shown in the illustration. figure 11. 63-ball plastic ball grid array (pbga) table 11. package diagram dimensions (mm) symbol min nom max symbol min nom max a 1.24 1.41 1.58 e1 7.00 bsc a1 0.40 0.50 0.60 e 1.00 bsc a2 0.34 0.38 0.42 s 0.50 bsc a3 0.50 0.53 0.56 aaa 0.10 b 0.50 0.60 0.70 bbb 0.10 d 9.00 bsc ccc 0.12 e 9.00 bsc ddd 0.15 d1 7.00 bsc eee 0.08 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing co nforms to jedec outli ne mo-192, variation aab-1. 4. recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components.
si5321-xc3 rev. 2.4 31 7. 9x9 mm pbga card layout notes: general 1. all dimensions shown are in millime ters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-7351 guidelines. solder mask design 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 1. a stainless steel, laser-cut and electro-polished stencil wi th trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1. card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ ipc j-std-020c specification for small body components. symbol min nom max x 0.40 0.45 0.50 c1 7.00 c2 7.00 e1 1.00 e2 1.00
si5321-xc3 32 rev. 2.4 d ocument c hange l ist revision 2.0 to revision 2.1 ? updated table 4, ?ac characteristics (pll performance characteristics),? on page 10. ? updated die length, die width, and substrate thickness specifications in ?package outline? and table 11, ?package diagram dimensions (mm),? on page 30. revision 2.1 to revision 2.2 ? updated table 2, ?dc characteristics, v dd =3.3v,? on page 6. ? added figure 4, ?typical si5321 phase noise (clkin = 155.52 mhz, cl kout = 622.08 mhz, and loop bw = 800 hz),? on page 14. ? updated table 11, ?package diagram dimensions (mm),? on page 30. revision 2.2 to revision 2.3 ? updated "6. package outline" on page 30. revision 2.3 to revision 2.4 ? updated "5. ordering guide" on page 29. ? updated "6. package outline" on page 30. ? updated "7. 9x9 mm pbga card layout" on page 31.
si5321-xc3 rev. 2.4 33 n otes :
si5321-xc3 34 rev. 2.4 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: clockinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and dspll are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and om issions, and disclaims responsibi lity for any consequences resu lting from the use of information included herein. ad ditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laboratories products ar e not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or use silicon laboratorie s products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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